1. general description the 74ahc374-q100; 74ahct374-q100 is a high-speed si-gate cmos device and is pin compatible with low-power schottky ttl (l sttl). it is specified in compliance with jedec standard no. 7-a. the 74ahc374-q100; 74ahct374-q100 comprises eight d-type flip-flops featuring separate d-type inputs for each flip-flop and 3-state outputs for bus oriented applications. a clock input (cp) and an output enable input (oe ) are common to all flip-flops. the eight flip-flops will store the state of their individual d inpu ts that meet the set-up and hold times requirements for the low-to-high cp transition. when oe is low the content of the eight flip-flo ps is available at the outputs. when oe is high, the outputs go to the high-imp edance off-state. operation of the oe input does not affect the state of the flip-flops. this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? balanced propagation delays ? all inputs have schmitt-trigger actions ? inputs accept voltages higher than v cc ? common 3-state output enable input ? input levels: ? for 74ahc374-q100: cmos level ? for 74ahct374-q100: ttl level ? esd protection: ? mil-std-883, method 3015 exceeds 2000 v ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) ? multiple package options 74ahc374-q100; 74ahct374-q100 octal d-type flip-flop; posit ive edge-trigger; 3-state rev. 1 ? 11 march 2014 product data sheet
74ahc_ahct374_q100 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 march 2014 2 of 18 nxp semiconductors 74ahc374-q100; 74ahct374-q100 octal d-type flip-flop; positive edge-trigger; 3-state 3. ordering information 4. functional diagram table 1. ordering information type number package temperature range name description version 74ahc374-q100 74ahc374d-q100 ? 40 ? c to +125 ? c so20 plastic small outline package; 20 leads; body width 7.5 mm sot163-1 74AHC374PW-Q100 ? 40 ? c to +125 ? c tssop20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 74ahct374-q100 74ahct374d-q100 ? 40 ? c to +125 ? c so20 plastic small outline package; 20 leads; body width 7.5 mm sot163-1 74ahct374pw-q100 ? 40 ? c to +125 ? c tssop20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 fig 1. functional diagram mna892 3-state outputs ff1 to ff8 q0 q1 q2 q3 q4 q5 q6 q7 19 16 15 12 9 6 5 2 d0 d1 d2 d3 d4 d5 d6 d7 cp oe 18 11 1 17 14 13 8 7 4 3
74ahc_ahct374_q100 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 march 2014 3 of 18 nxp semiconductors 74ahc374-q100; 74ahct374-q100 octal d-type flip-flop; positive edge-trigger; 3-state fig 2. logic symbol fig 3. iec logic symbol mna891 d0 d1 d2 d3 d4 d5 d6 d7 oe cp q0 q1 q2 q3 q4 q5 q6 q7 11 1 19 16 15 12 9 6 5 2 18 17 14 13 8 7 4 3 mna196 19 16 15 12 9 6 5 11 c1 1 en 1d 2 18 17 14 13 8 7 4 3 fig 4. logic diagram mna893 q4 d4 q3 d3 q2 d2 q1 d1 q0 d0 d ff1 q cp cp d ff2 q cp d ff3 q cp d ff4 q cp d ff5 q cp d ff6 q cp d ff7 q cp d ff8 q cp oe q5 d5 q6 d6 q7 d7
74ahc_ahct374_q100 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 march 2014 4 of 18 nxp semiconductors 74ahc374-q100; 74ahct374-q100 octal d-type flip-flop; positive edge-trigger; 3-state 5. pinning information 5.1 pinning 5.2 pin description fig 5. pin configuration so20 and tssop20 $ + & |